High-precision validation and multi-domain testing techniques for complex chipsets

With the proliferation of digital devices used in the consumer space, there has been an increased demand for performance and a concurrent growth in power and cost that needs to be effectively managed for sustaining the growth in the semiconductor industry. Chip manufacturers are continuously challenged with the need to reduce the risk of test escapes as they begin the migration at both the die level as well as the package level by incorporating unproven and unverified technology in production systems (Goldsmith, 2005; Biglieri, 2007; Heath et al., 2016). This is also being emphasized by the technology transition coming from 20 nm to 14nm and further migrations to 10nm and below where chip costs are extremely high and the silicon brought up is concurrent with product implementation timelines that necessitate the introduction of effective validation and testing strategies that are organized and method driven. As has been experienced in the past, as technology scales and design complexities increase, multi-domain functional testing of die with deeply embedded die-to-die and die-to-package interconnect circuitry becomes critical in ensuring adequate test coverage and reducing the risk of test escapes from manufacturing. Emphasis on the need for the early introduction of Validation and Fault Testing techniques is becoming increasingly important. We present techniques and concepts that help facilitate the reduced validation time frame and validate complex die with high density die-to-die and die-to-package interconnects and circuitry. These techniques are modular in implementation and can deal with complex test access challenges during silicon bring up and preliminary validation when standard boundary scan and serial link circuitry techniques cannot be reliably used.