Architectural trends in RISC-V, GPUs, TPUs, and domain-specific artificial intelligence accelerators

For years, the open-source RISC-V instruction set has been driving innovation in processor design. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. This unit should enable dynamic custom instruction sequence execution whose usage could be to compress binaries, obfuscate behavior, etc. RISC architectures are designed to integrate few instructions, thus lacking the micro-decoding mechanism. The open-source RISC-V ISA provides the compiler with about fifty elementary instructions. Many architectures implement this instruction set. Currently, high-end RISC-V processors feature 64-bit data paths, deep pipelines, and are capable of running a Linux-type operating system thanks to their advanced architectural optimizations (Ferrandi et al., 2023; Kalapothas et al., 2023; Alam et al., 2024). It is up to the compiler to identify the appropriate instruction combinations to generate efficient code. This inevitably leads to the production of larger programs compared to their CISC counterparts. For applications that would benefit from such an approach, the trade-off between CPU resources and code savings has been assessed. During the last decade, RISC-V has become a well-established open ISA standard. RISC-V is the fifth major RISC ISA design from the University of California Berkeley. The open ISA provides processor designers and implementers with the capability to innovate freely without intellectual property restrictions, thereby lowering the barrier to research and education beyond the historical reach of ISAs such as ARM, SPARC, and MIPS. RISC-V supports various essential features of an ISA: numerous high-quality open-source tool-chain components, including simulators, compilers, assemblers, linkers, and libraries, which are actively maintained; a simple instruction set design that can achieve excellent performance because of its simplicity; various instruction set extensions that are modularly designed and required based on clearly defined markets, and all the RISC-V ISA candidates are freely accessible; and extensive applications, with broad commercial, military, academic, and research adoption (Peccerillo et al., 2022; Klein, 2024; Tiwari et al., 2025).